1. Field of Use
This invention broadly relates to switching circuits suitable for semiconductor devices. More particularly, this invention relates to buffer circuits which enhance switching in digital gates using logic such as transistor-transistor logic (TTL).
2. Background Art
TTL circuits are derived from a common NAND logic structure such as the conventional arrangement seen in FIG. 1. In the TTL gate of FIG. 1, a set of logical input voltage signals represented by input voltages V.sub.I1, V.sub.I2, and V.sub.I3 are provided to the corresponding emitters of a multiple-emitter NPN input transistor Q1. The collector of transistor Q1 is connected to the base of an NPN phase-splitting drive transistor Q2 in a switching section of the gate. In fact, it is this arrangement which conventionally comprised the distinguishing feature of TTL circuitry. However, the definition of TTL has broadened over a period of time to include elements arranged in diode transistor logic and integrated injection logic format etc., as long as a bipolar device having certain input/output characteristics is provided.
Returning to FIG. 1, the base of transistor Q1 is connected to a current source consisting of a resistor R1 connected to a source of a high supply voltage V.sub.CC. The Q2 collector is connected to a current source formed by a resistor R2 tied to the V.sub.CC supply. The Q2 collector is further connected to the base of an NPN level-shifting transistor Q3. The emitter of transistor Q3 drives an NPN output pull-up transistor Q4 and is coupled through a resistor R3 to the emitter of Q4. The interconnected collectors of the Darlington pair Q3 and Q4 are coupled by a resistor R4 to the V.sub.CC supply.
The emitter of transistor Q2 is connected to the base of an NPN output pull-down transistor Q5 whose emitter is connected to a source of a low supply voltage V.sub.EE. A logical output voltage signal V.sub.o is provided from the interconnection of the Q5 collector and the Q4 emitter. An output pull-down resistor R5 is connected between the V.sub.EE supply and the base of transistor Q5.
The operation of the TTL gate of FIG. 1 may be understood by first assuming that each of the digital inputs V.sub.I1 -V.sub.I3 is at a high value (i.e. logical "1") above the input switching point. Transistor Q1 has its base-collector junction conductively forward biased This enables the R1 current source to provide current through the Q1 base-collector junction to the base of drive transistor Q2 so as to make transistor Q2 conductive. The R2 current source provides current through transistor Q2 to the base of transistor Q5 which is likewise turned on. With transistor Q5 turned on, the output voltage v.sub.o is pulled to a low value (i.e. logical "0") as the collector of transistor Q5 attempts to stabilize at a voltage equal to V.sub.EE +V.sub.sat, (V.sub.sat being the standard voltage drop from the collector to the emitter of a bipolar transistor
When an increase in the base current produces no change in the collector current). Also, with the collector of Q2 at a low voltage, transistors Q3 and Q4 are turned off. Hence, the output voltage V.sub.o is not affected by the high supply voltage V.sub.CC as the current path from V.sub.CC to the output is blocked.
If one of the digital input voltages V.sub.I1 -V.sub.I3 is dropped to a low value below the input switching point so as to conductively forward bias the corresponding Q1 base-emitter junction, transistor Q2 is turned off. With transistor Q2 off, the collector of Q2 goes to a high voltage (due to V.sub.CC) which causes transistor Q3 to turn on. In turn, transistor Q4 turns on and actively pulls voltage V.sub.o to a high value. At the same time, since transistor Q2 is off, transistor Q5 is turned off and the output is not affected by the low supply voltage V.sub.EE as the current path from V.sub.EE to the output is blocked.
While the output of the gate of FIG. 1 properly corresponds to the logical NAND of the inputs, various problems arise in the interaction of the integrated circuit gate with the integrated circuit voltage supply lines as well as with the circuitry which loads the output of the gate. With respect to the internal voltage supply lines, it is known that the voltages of these supply lines can "bounce", particularly when the logic transition of the input signal occurs at a high speed. One cause of "bounce" is that with the gate of FIG. 1, it is possible for a short period of time that both transistors Q4 and Q5 will be conducting. Thus, a low resistance feedthrough circuit from V.sub.CC to V.sub.EE via transistors Q4 and Q5 will be undesirably provided and will tend temporarily to force the low voltage supply line to assume a higher voltage as well as the high voltage supply line to assume a lower voltage until one of the transistors Q4 and Q5 is turned off.
Another cause of voltage supply line bounce is due to the capacitance of the circuit loading the output and the inductance and resistance of the V.sub.EE path. During a high to low transition at the output, a built-up charge on the gate output resulting from the capacitance of the load, quickly discharges through transistor Q5. A large current flow through the low resistance of Q5 and out onto the low voltage line causes a voltage drop on the line (i.e. "ground bounce"). Where a large change of current occurs quickly, the inductance of the low voltage line which is in series with the current path causes a change in voltage between the external V.sub.EE mains and the internal low voltage line in accord with the relationship .DELTA.V=L di/dt, where .beta.V is a change in the voltage, L is the inductance, and di/dt is the change in current over time. Similarly, during a low to high transition at the output, the high voltage line V.sub.CC will experience bounce as a large current will flow from the high voltage line through R4 and Q4 to charge up the effective capacitor of the load. In conjunction with the quickly changing current, the effective inductance of the V.sub.CC path will again cause a change in voltage between the external mains and the internal high voltage line.
Means for partially eliminating ground bounce for a TTL circuit are seen with reference to Japanese Patent Application No. 58-33051 of H. Ozaki, and U.S. Pat. No. #4,562,364 to T. Tanizawa. The Ozaki disclosure provides a circuit similar to that of FIG. 1, except that the collector of the phase splitting drive transistor is connected to both the high power supply V.sub.CC via a resistor and to the input terminal of a delay circuit. The output of the delay circuit is connected to the base of the first stage of the Darlington pair which acts as the high output driver. The delay circuit acts to delay the turning on of the high output driver until the low output driver is turned off, and thus eliminates the direct feedthrough current which could flow through the output driving transistors in a low to high transition. The delay circuit, however, does not eliminate possible direct feedthrough during a high to low transition. Nor does the delay circuit eliminate ground bounce caused by transitional currents due to the effective capacitance of the load as aforedescribed.
Turning to FIG. 2, the TTL circuit of Tanizawa which eliminates ground bounce due to direct feedthrough from V.sub.CC to V.sub.EE is shown. The circuit of FIG. 2 eliminates direct feedthrough by forcing the high output drivers (Tr.sub.2 and Tr.sub.3) off before the low output driver Tr.sub.4 is turned on and vice versa. When the input is high, transistor Tr.sub.5 conducts, and the low voltage output driver transistor Tr.sub.4 is on. At the same time, with a high input, transistor Tr.sub.6 is on, and its collector voltage is brought low such that it cannot drive Darlington pair Tr.sub.2 and Tr.sub.3. With transistor Tr.sub.4 on and transistor Tr.sub.3 off, the output D is held low. Upon a high-to-low transition of the input, transistor Tr.sub.4 will be turned off as soon as the input voltage drops below 2V.sub.be, where V.sub.be is the standard voltage across the base-emitter junction of a bipolar transistor when the transistor reaches full conduction in the forward direction. However, at a voltage of 2V.sub.be, transistor Tr.sub.6 will still conduct as the voltage drop v.sub.sch across Schottky diode D3 is less than v.sub.be. Hence, transistors Tr.sub.2 and Tr.sub.3 will remain off until the input voltage drops below V.sub.be +V.sub.sch, at which time transistors Tr.sub.2 and Tr.sub.3 start conducting and cause the output voltage to go high.
With the output high, when the input starts changing from low to high, the high output voltage driver transistors Tr.sub.2 and Tr.sub.3 will stop conducting as soon as the input voltage reaches V.sub.be +V.sub.sch, as transistor Tr.sub.6 will start conducting at that input voltage. However, the low output voltage driver transistor Tr.sub.4 does not turn on until the input voltage reaches 2V.sub.be. As a result, there is a time delay between the turning off of one voltage output driver and the turning on of the other voltage output driver, and except for the situation of a very quickly changing input, line bounce due to a feedthrough path is eliminated with the provided "break before make" circuit. Nonetheless, bounce due to the effective capacitance of the load on the TTL circuit is not eliminated by the Tanizawa circuit.